The present invention relates to digital delay lines in general, and more particularly to an improved variable length digital delay line.
Digital delay lines are well known, which are used to introduce a phase delay between two signals, in particular between logic signals each having two opposite logical states as a function of time. For instance, U.S. Pat. No. 3,588,707 of R. A. Manship uses a tapped shift register to create a digital time delay of various length.
It is also known from U.S. Pat. No. 3,760,280 of M. T. Covington to control the delay of an analog signal in response to a control signal by conversion through a voltage controlled oscillator into a binary signal which is frequency modulated, using a shift register as a delay line, which is actuated by a clock.
An object of the present invention is to provide an improved digital delay line.
Another object of the present invention is to use a random access memory device for providing a variable length digital delay line.